This application claims the priority of Korean Patent Application No. 2002-60814, filed 5 Oct. 2002, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a delay locked loop (DLL) circuit, and more particularly, to a DLL for internally correcting a duty cycle and a duty cycle correction method thereof.
2. Description of the Related Art
In data transmission such as between a memory device and a memory controller where data is transmitted after the data is synchronized with a clock signal, bus load and transmission frequency have increased. Thus, it is increasingly important to synchronize the data with the clock signal. That is, the time required to load the data onto the bus in response to the clock signal is compensated for to place the data at edges or centers of the clock signal. Between a phase locked loop (PLL) and a delay locked loop (DLL), the DLL is generally used in memory devices.
In a double data rate (DDR) interface where data is output at both a rising edge and a falling edge of the clock signal, the data interval output at the rising edge is different from the data interval output at the falling edge when the duty cycle of the clock signal is not 50%. In this case, timing margin is reduced because the valid data window for the clock transition is defined by a smaller data interval. Thus, a duty cycle corrector (DCC) is needed to correct the duty cycle of the clock signal.
FIG. 1 is a block diagram of a register-controlled DLL10 having a conventional DCC.
Referring to FIG. 1, the register controlled DLL10 includes a phase detector 11, a control circuit 12, a selection circuit 13, a delay chain 14, first and second phase interpolators 15, and a compensation delay 16.
DLL10 has a coarse loop and a fine loop. DLL10 uses the delay chain 14, i.e., a delay line, to control a delay for a coarse lock interval and uses the first and second phase interpolators 15 to control a fine delay for a fine lock interval.
In the conventional prior art, first and second phase blenders 17 are connected to an output end of the first and second phase interpolators 15 to generate internal clock signals DLCLK_F and DLCLK_S, whose duty cycles are corrected. The first and second phase blenders 17 each include two inverters 21 and 23, which have a common output end as shown in phase blender 20 of FIG. 2. Thus, a rising edge of an output signal OUT is generated between a rising edge of a signal IN1 input to the inverter 21 and a rising edge of a signal IN2 input to the inverter 23. In the same way, a falling edge of the output signal OUT is generated between a falling edge of the signal IN1 input to the inverter 21 and a falling edge of the signal IN2 input to the inverter 23.
However, a duty cycle correction method using phase blenders 20 has the following disadvantages. Firstly, the range of the DCC is related to the slopes of the signals IN1 and IN2. That is, the slopes of the signals IN1 and IN2 have to be gentle in order to facilitate the DCC, and thus large capacitance capacitors C1, C2, and C3 are connected to the input ends and the common output end of the inverters 21 and 23. If the duty cycle of an external clock signal ECLK has a ratio of 40 to 60 or a ratio of 60 to 40, the DCC may not perform properly, and power consumption increases, restricting the operating frequency. Secondly, since a delay exists in the phase blenders, a margin of a clock to valid output delay time (tSAC) is reduced.